SMT land structure technology & analysis

SMT land structure technology & analysis

The basic constituent elements of the surface mount assembly used to form the land pattern of the circuit board, that is, the combination of pads for the particular component type design. There is no worse than the design of the pad structure It is difficult and sometimes impossible to achieve the desired weld point when a pad structure is not designed correctly. The pad has two words: Land and Pad, which can often be used interchangeably; , In function, Land is a two-dimensional surface feature for surface mount components, and Pad is a three-dimensional feature for pluggable components. As a general rule, Land does not include plated through holes (PTH, plated through (via) is a plated through hole (PTH) that connects different circuit layers. The blind via connects the outermost layer with one or more inner layers and the buried bypass holes Only connect the inner layer.

As noted above, the pad Land typically does not include electroplated through-holes (PTH). The PTH in a pad Land will take a significant amount of solder during soldering and, in many cases, solder pads that are insufficiently solderable. However, in some cases, component wiring density forcing to change to this rule, the most noteworthy is the chip size of the package (CSP, chip scale package). 1.0mm (0.0394 ") spacing below, it is difficult to a The wires are routed through the "maze" of the pads. The blind vias and micro-channels are produced in the pads, allowing direct wiring to the other layer, since these bypass holes are small and blind, so they do not Will suck too much solder, the results of the solder the amount of tin is very small or no effect.

There are many industrial literatures available from IPC (Association Connecting Electronics Industries), EIA (Electronic Industry Alliance) and JEDEC (Solid State Technology Association), which should be used when designing the pad structure.The main document is the IPC-SM-782 "Surface Mount Design and Padding Structure Standard", which provides information on the pad structure used for surface mount components.When the J-STD-001 "Requirements for Welding Electrical and Electronic Assemblies" and IPC-A-610 "Acceptability of Electronic Assemblies" are used as solder joint process standards, the pad structure should conform to IPC-SM-782.If the pad deviates significantly from the IPC-SM-782, it will be difficult to achieve solder joints that conform to J-STD-001 and IPC-A-610.Component knowledge (ie, component structure and mechanical dimensions) is a fundamental requirement for the design of the pad structure. The IPC-SM-782 uses two components widely: EIA-PDP-100 "Registration of electronic components with standard mechanical form" And JEDEC 95 publication "Registration of Solid and Related Products and Standard Outline." It is indisputable that the most important of these documents is the JEDEC 95 publication because it deals with the most complex components. It provides all registration of solid elements And the standard profile of the mechanical map.

JEDEC publication JESD30 (also available for free download from JEDEC website) Defines the abbreviation of the component based on the characteristics of the package, material, terminal location, package type, pin form and number of terminals. Features, material, position, form and quantity The identifier is optional.

Package Features: A single or multiple letter prefix that confirms features such as pitch and contour.

Packaging material: a single letter prefix, confirm the main packaging material.

Terminal position: A single letter prefix that confirms the terminal position relative to the package profile.
Package Type: A two-letter mark that specifies the outline type of the package.

Pin New: A single letter suffix to confirm the pin form.

Number of terminals: a one, two or three digit suffix, indicating the number of terminals.
Surface Mount A simple list of encapsulation feature identifiers includes:
 E to expand the pitch (> 1.27 mm)
F spacing (<0.5 mm); limited to QFP components
 S contraction pitch (<0.65 mm); all components except QFP.
· T thin (1.0 mm body thickness)
Surface Mount A simple list of terminal position identifiers includes:
• Dual pins on either side of a square or rectangular package.
• The Quad pin is on the four sides of a square or rectangular package.
Surface Mount A simple list of package type identifiers includes:
· CC chip carrier (chip carrier) package structure
· FP flat pack (flat pack) package structure

· GA grid array (grid array) package structure

Small outline package structure
Surface Mount A simple list of pin form identifiers includes:
B is a straight handle or a spherical pin structure; this is a non-compliant pin form
F is a straight pin structure; this is a non-compliant pin form
 G A wing-shaped pin structure; this is a conforming pin form
A "J" -shaped pin structure; this is a conforming pin form
N is a pinless structure; this is a non-compliant pin form

An "S" -shaped pin structure; this is a conforming pin form

For example, the abbreviation F-PQFP-G208 describes 0.5 mm (F) plastic (P) square (Q) plane package (FP), winged pin (G), number of terminals 208.
Detailed analysis of the component and plate surface characteristics (ie, pad structure, reference points, etc.) is necessary. The IPC-SM-782 explains how to perform this analysis. Many components (especially dense pitch components) are strictly metric units Do not design an inch pad structure for metric components. The cumulative structural error does not match and can not be used for dense spacing elements. Remember, 0.65mm is equal to 0.0256 "and 0.5mm is equal to 0.0197".