Solder wire and paste feature| SMT Technology

Solder wire and paste feature| SMT Technology

Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper “sandwich” to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.

Solder voids in solder joints are a common occurrence in SMT assemblies. Their origins are not well understood but are typically faulted as a failure of the solder fillet to thoroughly expel flux remnants during the reflow process. The amount of solder voiding can vary significantly within an assembly, between different flux formulations, solder alloys, board and component metalizations. Reflow profiles as well as stencil aperture designs can often affect the overall level of voiding.

Adding to the mystery of solder voiding is a lack of quantitative measurement tools in the industry with few exceptions. BGA void analysis software is one of these exceptions. This software uses gray level pixel analysis to determine the perimeter of the solder sphere and the internal perimeters of the voids. Once the perimeters are established the areas within these structures can be measured and an overall percent voiding can be calculated. This type of measurement works well if the voids are large or found on the outer edges of the sphere but if the void is small and centrally located where the sphere density is the greatest then the void may be invisible due to its relatively similar gray level to the surrounding material. Increasing the X-ray power will reveal the small void but also shrink the measured area of the sphere and yield an inaccurate and inflated percent voiding. This problem is even more complicated in a chip or a leaded component solder joint. When X-raying a completed assembly, internal traces, vias and even components on the backside of the board that intersect the image of the solder joint confound the software algorithms ability to accurately determine the perimeter of the solder joint. In simple terms the X-ray image is two-dimensional and the ideal structure must be symmetrical about the Z-axis such as a box or a cylinder.

Novel Approach

Based on the assumption that the ideal quantitative void measurement method will utilize BGA analysis software and a symmetrical Z-axis reflow structure, the “sandwich” concept was developed.

This a novel approach simulates the worst conditions of a solder joint for voiding, under the component where flux evacuation is the most difficult while maintaining the same reflow thermal environment and metallurgies if desired. This idea was born out of a quest for a quantitative method of determining the percent voiding on a Ceramic Column Grid Array (CCGA)1. In the CCGA the columns are 10/90 Sn/Pb and cover about 45% of the solder fillet. If enough power is used to see through these dense columns, the perimeter of the solder joint is washed out and 55% of the total fillet is invisible. If adequate power is used to see the perimeter of the circular fillet, the area under the columns is invisible. The effort is complicated by column parallax, internal traces and vias as can be seen in Figure 1. With the thought of a column the same diameter as the solder pad that is thin enough to be X-rayed without excessive power, a solder preform was selected. In this application the preform alloy was selected to be the same as the 10/90 columns to minimize the variables that could contribute to solder voiding. Several thicknesses were tested with a 30 mil diameter by 5 mil thick as the final solution.

There were numerous challenges placing these discs. The first problem was a reliable source cup shaped and stacked discs were the first problems to solve. The second problem was the mechanics of actually placing the discs in that the vision systems in the pick and place were never programmed to recognize round components, only components with corners like typical chips. This relegated a “ballistic” pick and place strategy. For this problem a precision matrix tray with cylindrical pockets, each holding one preform, was developed as in Figure 2. Next came improvements to the pick and place nozzle. The stock smallest nozzle OD was the same as the preform. This presented numerous pick problems if the preform was not perfectly centered, occasionally the preform would flip on its edge after pick and crash on placement deforming the preform. Several improvements were made ultimately reducing the nozzle tip down to what would be typical for a 0201 chip as in Figure 3. Reducing the nozzle tip surface area helped eject the preform better in the placement operation.

Assembly of the CCGA test coupons is simple SMT assembly beginning with a “pads only” ceramic coupon to maintain the geometries and pad metalization of the application. This coupon is free of internal traces as in Figure 4. The solder paste is printed through a circular aperture that is 1 mil smaller in diameter than the pad, the preform is placed over the solder paste and then reflowed as in Figure 5. It was established that if the preform was off pad less than 4 mils that it would self-center. Careful attention to Z-axis placement is required to prevent shorting with adjacent preforms.

After assembly the coupon area was X-rayed and quantitative void analysis was performed on the image using off- the-shelf BGA analysis software as in Figure 6. This software provides both total percent voiding and a pass/fail status if any individual void within a structure is larger than a preset number (ie 5%). This technique worked very well for the custom formulated 63/37 Sn/Pb based solder paste or any other alloy with a similar melt point but when tested with lead free (Sn/Ag/Cu, Mp 219°C) it was noticed that the preforms had appeared to melt and partially join the underlying solder paste under test. This was remedied by switching to OFHC copper preforms of identical geometries. For generic paste void benchmarking2 a dedicated pad test area (Figure 7) was included in the Benchmarker II test board. This allows the testing of solder pastes on standard PCB surfaces such as Entek OSP (Organic Solder Protectant) and ENIG (Electroless Nickel Immersion Gold). Quite simply we are making copper sandwiches (Figure 8) that result in cylindrical structures, which permit highly quantitative void analysis with standard BGA analysis software.

rom this data there are clearly different trends for the two materials as well as a significant difference in void behavior between them. The effect of time on Material A is accelerated in cold storage and just the opposite with Material B. Both materials have the exact same source and specifications of the inorganics (powder + additives).

Profile Effects
The effect of the reflow profile can be significant but the magnitude varies greatly from one formulation to another. The following example involves two 63/37 Sn/Pb no clean materials3,4, tested over Entek passivated copper using the copper preforms with the 4 profiles as illustrated in Figure 10. This profile matrix is designed to expose profile sensitivity of a given formulation, in this case relating to voiding. There are two profiles with a ramp style preheat and two with a soak preheat. There are 2 profiles with a peak of 225°C with 60 seconds over liquidous and two hotter profiles with a peak of 240°C with an extended liquidous of 90 seconds. The X-ray data has been compressed into a single “point scale” to facilitate comparisons. These points (100 is best) are calculated .

How Does 3D AOI Increase Manufacturing Quality?

PCB suppliers in the automotive space are vastly accelerating their time to market by using automated optical inspection AOI systems during PCB assembly. However, this next‐generation technique is not limited in scope to the automotive industry – it has powerful implications for the entire PCB industry.

What is 3D AOI?
To best understand the benefits that 3D AOI offers, it's useful to compare it to its predecessor, 2D AOI. In the past, automated optical inspection processes allowed electronics manufacturers to identify workmanship defects and other issues during the final stages of PCB assembly.

In a typical AOI setting, a top‐mounted camera takes precisely measured photographs of finished circuit boards and compares the results to a highly detailed schematic file. Parameter differences that pass a certain threshold get flagged, and a human operator inspects the product in question.

The upshot of this process is that human operators no longer need to manually verify every parameter of a finished circuit board – for modern PCBs, that would take far too long. Now, a small team of operators can verify a very large volume of PCBs and pick out the defective ones with great accuracy.

3D AOI builds on this premise by using two cameras to develop a three‐dimensional image of the PCB. This allows the AOI process to verify smaller components than ever before. In some cases, the addition of a side‐mounted stereo camera set lets the optical image technology build a complete render of the PCB, allowing for unprecedented precision and quality control.

Who Uses 3D AOI for PCB Inspection?
As of mid‐2017, this technology is almost exclusively used in the autonomous vehicles industry. The ability to quickly identify and measure panel defects when dealing with extremely small components is an important factor contributing towards making autonomous vehicles an everyday reality.

However, as time goes on, this inspection process will become more commonplace, vastly reducing the time and energy spent on PCB inspection. Manufacturers are continually looking for better, more efficient test methods that offer real‐time feedback. This way, PCB defects can be identified early in the manufacturing process, saving customer grief and company reputation by preventing potential recalls or, in some industry sectors, lawsuits.

When combined with laser direct imaging (DI) technology, AOI improves yield by minimizing expensive material waste. The combination increases the traceability of the supply chain and helps manufacturers identify the factors that generate production failures.

The PCB Used In Marine Industry Paving Way For Innovations

The PCB Used In Marine Industry Paving Way For Innovations

As the technology has become a universal key to major developments, the marine and boat industry has shown elevated growth in recent time. The marine market circumscribes on the electronic and design solutions for every single innovation. All the developments in Marine sector has and are heading towards a notion of modernization and among these, printed circuit board is grounding the research and developments. How to increase the efficiency of the device? How to gain optimum fuel efficiency? Does the dual fuel concept become a buzz word for major innovations? These are the basic questions which are considered to bring new novelties in the market. This article is a detailed conspectus of marine and boat industry and the role of printed circuit boards in manufacturing modified marine electronic instrumentation. This will also drive you to the spotlights into the use of PCB prototypes, PCB assembly and PCB Design in Maritime industry, the commendable marine innovations/ New concepts and the prime factors affecting the modernization in the marine industry.

Awash with modernization, the marine market shows innovations in safety devices, telematics, equipments with resistance to vibration, underwater marine machinery and many more. The marine and boating industry shows a major concern for the protection of electrical resources from destruction due to climatic reactions and global warming. With this, the Submarines, weather sensors, marine gauges, underwater equipment, crane, flood detector, galvanic Isolator, fuel efficient motors and other tough marine applications need proven design to engineer the marine vessel manufacturing.

The electric connectivity and mechanical support provided by marine PCB’s is at the base to create an all to gather efficient Marine machinery and aquatic vessel. From manufacturing ship, yachts, craft and other aquatic vessels depend on printed circuit boards to control the marine mechanism with electronic process. Among all, Rigid/Flex PCB is majorly used in providing electronic solutions that have an efficient RF Module. The maritime electronic PCB are of many types depending upon the purpose of use. The double layered and multi layered PCB is used for complex compositions of marine vessels. Also high grade PCB material is used in the circuit board that well suits the climatic reactions in the sea. The PCB is at the base of every single marine innovation happening across the globe. To explore more insights into the PCB used in the Marine industry, it is equally important to know about the current Maritime industry.

Initially the marine market marked stagnation before few decades. Gradually, with a drift in technology, the boat and marine industry has picked up a pace with new developments. This can be marked in marine civil construction and engineering, underwater ad diving technology, marine equipment, marine electronics, renewable energy and marine security. The research for developments in maritime sector has added crowns in the small devices and large equipment as well. Few developments seen in small marine devices are outlined as under:


Marine load testing is an electronic portable equipment with strong hydraulic cylinder and customized ropes to create more than 120 tonnes of pull underwater. The underwater Impact torque device is a marine electronic tool to strongly tighten the screw and nuts to perfect torque. The saltwater pressure washer that works with the help of Diesel and is extensively used for maintenance and cleaning of wind farms. The design and structure of the machine is such that has resistance to the marine conditions and can efficiently wash the offshore wind farm. The radio combiner and other marine telecommunication devices have an ergonomic design for compact high speed craft.

Apart from these, boat/ship dashboards, exit lights, marine spotlights, navigation system, electronic counter measurement device, engine management, radar system, beacon and strobe system have markedbreakthrough modifications to make it a fuel efficient and time savvy marine operations.

Recent Concepts:
0The Advance Outfitting is the time and cost saver technique to manufacture the ship and heavy marine machineries. In this method, the ship building process involves assembling the marine outfits like seating, piping, machinery in a small unit which is fixed at its actual position afterwards in the hull block. This saves much time and cost as before the ship building process the hull is fabricated first and after launching the hull from the berth, the outfitting process starts that proves to be tedious and time consuming.

The Green Ship Technology to reduce the carbon is a step ahead to environmental protection. It has a solar cell integration with effective anti ballast system. For making marine operations greener, many other marine electronic devices are launched in the market that includes the optimized cooling system, engines to bring down the level of nitrogen oxide level, exhaust scrubber, solar cell hybrid system, dual fuel motors and many more.

Be it a new or an old concept driving the marine operations, few factors affect the modernization in Marine innovations. Among which the Environment is a top most factor of prime consideration. Another aspect that brings a Dinger in the maritime industry is making a move towards Digitalization of all the marine operations. At the end, researchers are now striving to trigger the innovations in electronic instruments and control system that has high applicability in the Marine industry. Among which the different types of PCB prototypes and PCB assembly services are grounding the studies to come up with better and better solutions for marine machine manufacturing.

More details of SMT Technology,pls refer to : Joy Technology Co., Limited

Advanced modelling technique achieves near to zero set up time and minimal tuning

Advanced modelling technique achieves near to zero set up time and minimal tuning

Automatic Optical Inspection (AOI) is now an established solution for the reliable inspection of printed circuit boards (PCB’s) in the electronic manufacturing industry. AOI systems have developed considerably since their introduction in the mid 90’s, and now appear on most surface mount technology (SMT) production lines World-Wide. The majority of AOI systems utilize standard vision analysis technology in the form of multiple controlling algorithms and although there are many variations of this approach most are “programmed” and “tuned” in the same way. Modelling technology however is completely different in that it does not use a standard algorithmic approach but calculates process variation in real time on real production data by analysing pixel by pixel the image of the real production PCB. First conceived in the mid 1990’s and extensively developed since

Modelling is based on Principle Component Analysis (PCA) and has many advantages for companies looking for a fast and versatile system that can be deployed to production very quickly and with the minimum of on-going production tuning.

Importance of fast set up & minimal tuning time

One of the key metrics when selecting AOI solutions is the total cost of ownership of the system once deployed to production. Programming time and production tuning time are major contributors to the on-going ownership costs hence should be measured and understood well in advance of production integration. In low volume / high mix applications set up time is even more important as the AOI program has to be ready and capable of reliable inspection before the production run is complete to have any real value. With production batch sizes below 20 x PCB’s this is very difficult to achieve on most algorithm systems.

Limitations of Algorithm technology approach for fast set up

Most algorithm technology systems are set up with the user having to anticipate the possible range of defects that could occur in production. The set up process includes selecting combinations of algorithms and setting their parameters in addition to those controlling image acquisition. This can be very time consuming with careful attention required to ensure everything is set up accurately.

Advantages of modelling technology for controlling process variation

Statistical Appearance Modelling technology is set up very easily and simply from an image of the first production PCB. The system “learns real world variation” based on operator interaction with the reported results of the inspection tasks. This results in a very accurate statistical description of the normal variation in the product. Using this description during inspection allows accurate reporting of what is acceptable and what is not acceptable to the user based on individual process or quality requirements. Clear advantages of this approach are that the user does not have to anticipate potential defects or process issues as the system will “flag” anything that is outside of the “normal production range” and secondly because the system is programmed with real production variation it is very sensitive to small subtle changes enabling very reliable defect detection. Recent developments to this technology include autonomous prediction of process variation which enables the AOI system to be set up from a single PCB with production ready performance. Set up time can


be as low as 15 minutes from data input to first PCB inspection making it extremely attractive for new product introduction (NPI) and first off verification.


Performance comparison of modelling technology versus Algorithm technology

The tables below are results taken from a recent production evaluation in the Automotive Industry. The PCB tested is a 6 up panel 300mm in length and 260mm in width with a total component count of 1380 and 73 individual component types. The inspection set up included tasks to reliably detect all component body, position, text, value, and solder joint related defects and the total individual inspection task count was 8,307

Table 1 below clearly illustrates a significant performance advantage of the modelling approach versus algorithm technology on this application with results of up to 3 x faster set up time for the modelling system. Of course a fast set up is only advantageous if the system can reliably inspect PCB’s afterwards with a very low false failure rate and provide some immediate value to the user

Table 2 below again illustrates a significant advantage from the modelling system when counting false failures after programming from 1, 10, and 30 panels. Again the modelling system was around 3 x lower in false failure rates.


AOI systems have developed considerably over the past twenty years and with the constant advances in computational technology there is no doubt that this pace of development will continue. Modelling technology is a key area of image analysis that is benefiting from these advances and is already a very attractive alternative to traditional algorithm technology when applied in SMT inspection.

With the ever increasing demand for faster set ups and improved inspection performance on a wide range of applications, statistical modelling technology is a very interesting and valuable solution especially where set up times and cost of ownership are critical to success.

How to calibrate smt feeder | technology

How to calibrate smt feeder

SMT feeder is used for a long time, there will be accuracy error, it needs to be calibrated to ensure that smt feeder work more smoothly and more efficient, the following describes the process of smt feeder calibration.

1.Choose a feeder with best chip-placement ratio, install the Calibration Ruler on this feeder, then place feeder to calibration equipment’s position table.

2.Adjusting the focus-distance H-Axis makes display position centeral on FEEDER component, display show cross cursors in the middle of intersection, make it clear then lock tight, readjust X, Y -Axis makes display position centeral on FEEDER component -eyelet centeral in the middle of intersection, and lock tightly. Then prepare work have complete, please never adjust X, Y, H- Axis again.

3. Remove the FEEDER with Calibration Ruler from calibration equipment, Place the calibration ruler into the feeder need adjust and set up to the Jig position, press Auto/Manual key observe cross cursor centeral whether component cross place to superposition together, if not, please adjust FEEDER bolt-pin to make with display superposition together.Check once wheel gear, and lock screw tightly.

4. How to adjust bolt-pin of the feeder?

a） Adjust Y-Axis: loose screw in Picture A & B, then turn pin in Picture C to adjust Y-Axis, after adjustment completed, pls lock the screw in Picture A & B tightly:

b） Adjust X-Axis:: loose screw in Picture D & E, then turn pin in Picture F to adjust X-Axis, after adjustment completed, pls lock the screw in Picture D & E tightly.

More details refer to : Joy Technology Co.,Limited

2.5D and 3D Semiconductor ---SMT Technology

The electronics industry is experiencing a renaissance in semiconductor package technology. SMT technology is very important，a growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline, product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability. Multiple die packaging commonly utilizes some form of substrate interposer as a base. Assembly of semiconductor die onto a substrate is essentially the same as those used for standard I/C packaging in lead frames; however, substrate based IC packaging for 3D applications can adopt a wider range of materials and there are several alternative processes that may be used in their assembly. Companies that have already implemented some form of 3D package technology have found success in both stacked die and stacked package technology but these package methodologies cannot always meet the complexities of the newer generation of large-scale multiple function processors.

A number of new semiconductor families are emerging that demand greater interconnect densities than possible with traditional organic substrate fabrication technology. Two alternative base materials have already evolved as more suitable for both current and future, very high-density package interposer applications; silicon and glass. Both materials, however, require adopting unique via formation and metallization methodologies. While the infrastructure for supplying the glass-based interposer is currently in development by a number of organizations, the silicon-based interposer supply infrastructure is already well established.

This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources, roadmaps and market forecasts.

Key words: 2.5D, 3D Semiconductor Package Technology, Through Silicon Via, TSV, Through Glass Via, TGV

Introduction
A majority of the semiconductor die elements continue to be designed with bond sites at the perimeter edge. For a wide range of applications, both single and multiple die-stack package assembly processes will likely continue to employ conventional face-up die attach and wire-bond methodology. The use of wire-bond interconnect as the exclusive means of termination, however, is somewhat restrictive because it requires significant surface area to accommodate the die-to-interposer wire-bond process. In regard to die-stack package assembly, managing the layout of several hundred interconnects and their wire-loop profile restrictions will entail a great deal of planning.

Even though a great deal of progress has been made in process refinement and system development, methodologies will vary a great deal. To ensure a strong infrastructure for 2.5D and 3D applications the industry will need a degree of harmonization and standardization. There are a number of multiple die package issues that will need to be resolved, including;

Selection of suitable component functions for multiple die packaging

Establish a reliable source for semiconductor elements

Specify physical and environmental operating conditions

Define package design constraints and understand process protocols

Stipulate electrical test method and post assembly inspection criteria

3D Semiconductor Package Innovations

Within the current decade the industry has developed an impressive family of multiple die solutions. A majority of the innovations utilized the existing package manufacturing infrastructure while others require the development of specialized materials and process systems. The organic interposer base will likely remain popular for a significant number of multiple die applications. To enable more efficient processing of multiple die sets, the substrates are furnished in a panel or strip format. In regard to assembly, when stacking two or more semiconductors onto a single interposer substrate for wire-bond assembly, the die elements will ideally have a progressively smaller outline. This tiered or pyramid die format has been very successful, generally furnishing the lowest overall multiple die package profile.

In this configuration, each die element is sequentially attached on top of one another. The progressively smaller die outline leaves the edge of all die elements accessible for wire-bond processing in a single operation.



Following molding operations, alloy ball contacts are commonly applied in the now familiar array format on the opposite surface of the interposer to accommodate electrical test and the eventual mounting of the finished package on the next level assembly. Because these heterogeneous die elements are mounted onto a single high-density interposer structure, the primary signal paths can be very short, contributing to increasing operating speed and power reduction. Although multiple die package technology has reached a level of maturity, package assembly yield may be adversely impacted when one or more die in the stack do not perform to their expected level or fail altogether.

When die elements have the same outline or nearly the same outline, thin silicon spacers are added between die elements to accommodate wire-bond loop heights. The example furnished in Figure 2 represents a stacked die assembly using a number of semiconductor die elements having the same outlines.


Excessive overall package height can be a critical roadblock for a number of personal hand-held product applications. For example, same size die elements generally represent memory functions. Unlike the tiered die assembly noted above, the memory die-stack process is less efficient. Although all memory die elements are assembled onto a common interposer base, die-attach and wire-bond operations for each die element must be completed before progressing to the next level. Even though the die elements can be made very thin, the accumulated stack-up height generated by the added spacer and wire-bond loop profile may not meet all package profile requirements.

3D Package-on-Package Solutions for Heterogeneous Applications

Combining the memory and logic functions in a single package outline has often compromised both test efficiency and overall package assembly yield. Vertically mounting one or more pre-packaged die elements (package-on-package) has evolved as a preferred alternative to die stacking, especially for applications requiring multiple heterogeneous semiconductor elements and, separating dissimilar logic and memory functions has proved to be very efficient. The logic die element often have a significantly larger outline and a greater number of I/O than the memory elements. For this reason, the base or lower package section will typically accommodate the logic while the memory functions associated with the logic die will be

deployed to the upper section of the package. Additionally, the package sections may utilize both wire-bond and flip-chip assembly methodologies. The flip-chip assembly will enable significant in-package interconnect capability and provide a very low package profile for the bottom section. This design illustrated in Figure 3 allows the mold material to extend out to the edge of the interposer on the lower section to minimize package warp and utilizes a through-mold-via (TMV) enabling smaller and closer pitch contact features between the upper and lower section.

Even though two substrate interposers are required for the PoP application, the joining of individually tested package sections have proved more economical.

Many of the more advanced 3D package solutions involved a great deal of engineering resources before they were made available for volume manufacturing and, although widely available, some variations will require licensing agreements with the developer before use.

Bond Via Array PoP

To overcome the limiting aspects of the more traditional PoP assembly method shown above, an alternative high-density substrate interconnect solution has evolved. The bond via array process enables a substantial reduction in interface contact pitch between the lower and upper package sections. The main feature of the bond via array concept is the use of commercially available organic based substrate materials and conventional wire-bond systems to furnish the closely spaced narrow copper-post contacts that provide electrical interface between upper and lower package sections. The detail shown in Figure 4 illustrates the upper and lower sections of the bond via array package.

Evolving 2.5D Interposer Technology

New semiconductor families are emerging that demand greater interconnect densities than possible with today’s organic substrate fabrication technology. Two alternative base materials have already proved to be more suitable for the both current and future very high-density package applications. The two base materials with the physical attributes considered most capable for the very high-density interposers are silicon and glass. Both materials, however, require adopting unique via formation and metallization methodologies to enable the interface between one side of the interposer to the other. The term

through-silicon-via (TSV) is applied to miniature ablated and plated via features in the silicon-based interposer. Likewise, furnishing similar features on the glass-based interposer is referred to as Though-Glass-Via (TGV). While the infrastructure for supplying the glass-based interposer is progressing, the silicon-based interposer supply infrastructure is already well established.

Silicon Interposer Fabrication
A great deal of resources have already been invested to bring TSV into a viable interconnect solution for both 2.5D interposers and 3D stacked-die assembly. In preparation for TSV, small diameter holes are first formed on one side of the silicon wafer. The most common process for this operation uses a deep reactive-ion etching (DRIE) process The via ablation process is also known as ‘pulsed’ or ‘time-multiplexed’ etching, a process that alternates repeatedly between two modes to achieve nearly vertical hole structures. During the pulsed etching process a passivation layer is naturally formed onto the vias sidewall to block further chemical attack and to prevent additional etching within the via sidewall. These etch/deposit steps are repeated until the ablation reaches the desired depth 

Although it is possible to etch via holes all the way through the silicon base, it is common practice to stop the etching process at a predetermined depth that will better promote via filling during the metalization process.

In preparation for via filling a seed layer of copper or tungsten is first applied to enable electroplating the additional copper required to complete the via fill operation. Electroplating is commonly employed for via sizes that range between 5μm and 20μm. To finally access the metallized Cu filled vias on the opposite surface of the wafer, a combination of grinding and/or plasma etching processes are utilized. Further pattern plating processes are finally employed to provide surface interconnect features as illustrated 

Because of its low resistivity and conductive characteristics, copper (Cu) has become the favored alloy for interposer via and circuit plating. In preparation for forming the Cu component termination sites (land patterns) and conductors on the silicon wafer surface, the fabricator will first sputter a metal alloy adhesion layer on the wafers surface. Adhesion-promoting metals include: nickel (Ni), molybdenum (Mo), chromium (Cr), tungsten (W), and titanium (Ti). These base materials are then over-plated with a more conductive metal such copper, gold, tin and palladium. Following the pattern plating the remaining thin adhesion layer is chemically etched from the silicon wafer surface followed by the application of a photo-imaged passivation 60μm

contact features located on the individual die elements may have a pitch as small as 30μm to 50μm, while the contacts on the bottom surface of the Si interposer are ‘fanned out’ to a wider 150μm to 200μm pitch. The illustration shown in Figure 9 is typical of silicon or glass interposer enabled 3D system level product with related but heterogeneous semiconductor die elements.




The wider pitch contact pattern on the bottom surface of the Si-based interposer will better accommodate solder ball or solder bump contacts for reflow solder attachment to the top surface of the organic based package substrate.

Three accepted methodologies for joining high-density semiconductors to the silicon-based interposer include 1) solder reflow processing, 2) thermo-compression bonding and 3) annealed copper bond interconnect 

Reflow soldering- The contact furnished for the very fine-pitch die-to-interpose attachment process is a ‘solder capped’ copper post or micro-bump contact. Key solder process issues include optimizing reflow temperature profiles, flux activation and time above liquidus (TAL). Because the standoff dimension between die and interposer surface can be 50 microns or more, underfill is commonly specified to reinforce the site. Flux selection can also be a factor. Any remaining flux residue that accumulates on the interposer surface during the solder process can promote excessive voids in the underfill.

Thermo-Compression Bond (Cu/Sn/Cu Fusion)- A two-stage procedure that begins with the initial precise alignment and room temperature pre-bonding of the die element to the interposer wafer. Following pre-bond, the interposer is exposed to an annealing process that includes high temperature and pressure. This joining process is significantly enhanced with the deposition of a thin layer of tin-alloy onto the exposed copper contact features. When the wafer interposer is heated to approximately 400oC, the tin alloy layer completely diffuses into the apposing copper contact features to form a stable Cu-Sn- Cu (Cu3Sn) intermetallic.

Low Temperature Hybrid Bond Technology- A heterogeneous or hybrid joining process furnishing an In-Situ electrical interface with patterned metal alloy contact surfaces and silicon oxide dielectric (e.g., Cu/SiO-Cu/SiO, Cu/SiN-Cu/SiN). This is a simple Cu-Cu bond that is scalable to a much finer contact pitch (< 30μm). Furthermore, when the die element is bonded

to the silicon interposer there is no remaining air gap so application of underfill between surfaces is not required. The direct bond interconnect process is also being utilized for thin wafer-to-wafer joining as well as joining singulated die prepared with aligned TSV contact features. The actual Cu-Cu annealing process for this requires a relatively short exposure time at a moderate 200 oC temperature.

Summary and Conclusions

While developers continue to explore alternative semiconductor package assembly methods to further improve yield, significant challenges remain for the newer generations of high-density and high I/O semiconductors. Although high volume consumer electronics will continue to drive similar forms of 3D package technology, high-end Telecom markets will rely on more sophisticated solutions. New generations of memory products have emerged with 30 micron pitch and two-thousand I/O and processors are entering the market that have forty-thousand I/O. To meet the requirement for interconnecting these very large, high I/O die elements, analysts and industry roadmaps predict that companies will continue to migrate toward silicon-based or glass-based interposer technology. Although many process issues have been resolved, there are a significant number of technical issues that influence this segment of the industry. The handling and transport of the large and very thin wafers, solutions for aligning and joining very high I/O die elements, and, when the system level package is incorporated into the end product, methodologies for managing thermal dissipation.

The decision on which interposer base material is selected will be dependent on process maturity, supplier capability and cost. In order to expedite product development many are partnering with suppliers at both the frontend and backend of the semiconductor supply chain. They realize that in order to bring 2.5D and 3D package technology into the forefront they will need to develop viable and robust, high yield wafer level interposer processes.

Analysis on the Function of SMT Nozzle

Analysis on the Function of SMT Nozzle

SMT nozzle In order to meet the usage requirement, when people in the design of the nozzle, the SMT nozzle touching elements are usually designed to the center of the symmetrical shape, and as the background of the nozzle face design designed to matte And the surface is not mixed color, of course, this background is usually designed as a single color, such as yellow and black.

Rust - proof lubricants
SMT nozzle is not only the placement of the components of the device to paste, put the key parts of the action, but also the optical vision system camera background, it is mainly the use of vacuum adsorption to the components to absorb, and Use the blower to put the element attached to the nozzle into the coordinate position of the circuit board.

When the nozzle to absorb the components, to achieve the ideal situation must ensure that the center of the component, the center of the nozzle and the image of the center of the space should be coincident, and optical vision system adjustment is actually Compensation for the actual work of the case does not coincide with the deviation caused.

Different mounting elements need to be sucked with different suction nozzles. Almost every nozzle will have a reflective background, which is primarily intended to have a good background for image pickup to ensure accurate information on the target when the image is processed Protruding, nozzle When extracting an image, the nozzle as a background, so that the component image contrast enhancement, more clearly visible.


(1) nozzle wear, nozzle deformation, clogging, damage caused by insufficient pressure, resulting in suction components, so to regularly check the degree of wear of the nozzle, the serious to be replaced.

(2) the impact of the feeder, the feeder feed bad (feeder gear damage), material hole is not stuck in the feeder gear, the feeder below the foreign body, card spring wear), pressure Cover plate, spring and other operating mechanism to produce deformation, rust, etc., resulting in components sucking, standing or sucking device, it should be regularly checked, to deal with, so as to avoid a large number of device waste.


(3) vacuum negative pressure is insufficient, when the nozzle to take the component, the nozzle at a certain negative pressure, the components adsorbed on the nozzle, the nozzle to pick up the components are unusual use of negative pressure detection mode, when the negative pressure When the sensor detection value is within a certain range, the machine thinks that the suction is normal, otherwise it thinks that the drawing is bad, and when the element is sucked, the vacuum negative pressure should be above 53.33kPa so as to have enough vacuum to suck the component.If the vacuum negative pressure is insufficient, Will not be able to provide enough suction to absorb the components, in use, we must always check the vacuum negative pressure, and regularly clean the nozzle, but also pay attention to each placement of the vacuum filter on the head of the pollution, its role is to reach the suction The mouth of the gas source to filter, to be black to be replaced, to ensure the smooth flow of air.

(4) to absorb the height of the impact of the suction nozzle is the ideal height of the suction nozzle is exposed to the surface of the component and then down the pressure 0.05mm, if the pressure is too large, it will cause the component is pressed into the tank instead If the absorption of an element is not good, it may be appropriate to adjust the height of the suction up slightly, for example, 0.05mm. The author in the actual work process has encountered a material on all the components are not well Of the situation, the solution is to system parameters in the material extraction of the height of the appropriate move up a little.

(5) nozzle to the incoming problem, some manufacturers of chip components packaging quality problems, such as large spacing between the teeth, tape and plastic film between the sticky is too large, too small trough size are Causing the possible cause of the component can not be taken.